1. Field of the Invention
This invention relates to 3D interconnects for wafers, printed circuit boards (PCBs) and other high density circuits and more specifically to a shielded through-via that reduces the effect of parasitic capacitance on a high impedance signal passing through the through-via.
2. Description of the Related Art
Via connectors are widely used in the electronic industry for making electrical connections between the opposite surfaces of electronic devices. For example, in the manufacture of printed circuit board assemblies it is common practice to place discrete electronic components on one surface of a printed circuit board and to form the required connecting circuitry, ground planes, or the like on the opposite surface with the required electrical connections being made through the printed circuit board by using plated through holes or by various other techniques well known to those skilled in the printed circuit board art. Via connectors are also used to make electrical connections between layers of a multi-layer laminate PCB.
In the fabrication of semiconductor devices, it is also often desirable to form solid state electronic components on one surface of the semiconductor wafer and connecting circuitry, ground planes or possibly other solid state electronic components on the opposite surface of the semiconductor wafer and then to provide electrical connections between the elements on the two surfaces. For example, in the manufacture of microwave devices, it is often desirable to form a field effect transistor or a diode on one surface of a semiconductor wafer, a microstrip, heat sink, ground plane, or the like, on the opposite surfaces of the wafer and then to provide the required electrical connection between the surfaces with a via connector. It is also often desirable to form multi-layer metal interconnects in a dielectric thin-film on one side of a substrate to provide electrical connections for the integrated circuitry and to provide the required electrical connection between metal layers with a via connector.
A three-dimensional (3D) wafer-to-wafer vertical stack technology seeks to achieve the long-awaited goal of vertically stacking many layers of active IC devices such as processors, programmable devices and memory devices inside a single chip to shorten average wire lengths, thereby reducing interconnect RC delay and increasing system performance.
One major challenge of 3D interconnects on a single wafer or in a wafer-to-wafer vertical stack is the through-via that provides a signal path for high impedance signals to traverse from one side of the wafer to the other. Commonly, holes are formed in the wafer, an oxide layer is deposited in the hole to insulate the through-via from the wafer, and the conductive via is deposited. The signal can be loaded by having to drive the parasitic capacitance formed between the through-via and the surrounding wafer and can be distorted by crosstalk from other signals reflected back onto the through-via through the parasitic capacitance.
U.S. Pat. No. 6,762,076 forms vias for wafer-to-wafer stacking by selectively etching the top wafer to form a via, depositing an oxide layer to insulate a sidewall of the via, forming a barrier/seed layer in the via, depositing a barrier layer in the via, depositing a seed layer on the barrier layer, and depositing a conduction metal on the seed layer in the via for providing an electrical connection between active devices on the vertically stacked wafers and the external interconnect. Vias taper from top to bottom so that a top surface of each via has a larger area in order to vertically stack wafers and connect the vias.
U.S. Pat. No. 5,949,030 forms multiple vias coaxially or in axis parallel alignment in a primary through-hole in a printed circuit board, chip carrier or like electrical device to increase the through via density to increase the I/O capacity of the devices. A primary metallized through hole or via is filled or coated with a dielectric material which is also placed on both surfaces of the device at the ends of the via. The dielectric material inside the via can then be provided with at least one coaxial through-hole or multiple axis parallel through holes which can be metallized to form conductive paths between the surfaces of the device. Portions of the dielectric surface layer can be removed to expose contacts to the inner metallized via. In addition electrical signal paths can be isolated within voltage or ground co-axial conductors.
Signal generating devices such as accelerometers, gyroscopes and pressure sensors can have a total capacitance of <1 pF. At typical frequencies, the signal impedance will be from 10 s of kilo ohms to giga ohms. To detect very small changes in the total capacitance, <1 fF or even <1 aF, the signal can not be loaded by the parasitic capacitance of the wafer structure or crosstalk with other electrical signals as it traverses the through-via. Alternately, a signal generating device such as a CCD camera is characterized by very high impedance (low capacitance) for each imaging pixel where the amount of charge on each pixel is changing. To detect small changes in charge, the signal must again be preserved. Furthermore, loading increases power consumption and heat dissipation. The challenge remains to provide a through-via that reduces and preferably eliminates the effect of parasitic capacitance formed between the through-via and the surrounding wafer and provides high isolation from other signals.